1. Field of the invention
The present invention relates to CMOS integrated circuits operating at relatively high voltage and, in particular, to a circuit arrangement for protecting p-channel transistors from the "gated breakdown" phenomenon.
2. Description of the prior art
In EEPROM and EPROM memory devices, particular circuits are often implemented for converting a logic signal having a range 0-VCC in a logic signal having a range 0-VPP, where VCC is the supply voltage of the general circuitry whereas VPP is a relatively high supply voltage (generated outside or inside the integrated device by means of a suitable voltage multiplier) used in programming circuits of the nonvolatile memory cells. Such a VPP voltage is normally much higher than VCC and often creates problems of junction breakdown particularly difficult to overcome when the fabrication process of the device is not designed for high voltage withstanding.
In general CMOS logic circuits are characterized by having pairs of p-channel and n-channel transistors connected in series between the supply rail and the ground rail of the circuit in order to have a current flow only on transitions while in steady state conditions one or the other of the two, opposite polarity transistors is cut off and prevents the flow of current (energy dissipation).
Going back to the specific problem raised by the necessity of utilizing a high level (VPP) supply voltage within limited portions of the CMOS integrated circuit, such a problem may be easily described for the case of an inverter (FIG. 1), wherein the output signal is the negative of the input signal, and for the case of a latch (FIG. 2), wherein the input signal is stored and the output signal is available in a direct as well as in a complementary form. These circuits may be considered representative of CMOS logic circuitry.
Usually the operation of these circuits at a relatively high voltage (VPP) contemplates that switching occur when VCC=VPP, after the VPP increases, more or less gradually to a maximum asymptotic value which is maintaned for a period during which no switching occurs. During the raising of the VPP voltage, one or more junctions of the integrated circuit may reach their breakdown voltage causing malfunctioning of transistors.
The inverter of FIG. 1 operates as follows. When the input IN is low, the node A is similarly low because the transistor P2 is usually much more resistive than the driver (not shown in the figure) which drives the signal applied to the input IN, and therefore the voltage at the output OUT rises to a VPP value (which at the transition instant is equal to the supply voltage VCC of the general circuitry), thus cutting-off the transistor P2 and confirming the logic zero on the node A. When the input IN becomes high (i.e. is forced to the VCC level), on the node A a maximum voltage equal to the supply voltage VCC less the threshold of the transistor N3 is obtained, and if this voltage raises beyond the threshold value of the inverter, the output OUT drops to zero, causing conduction of transistor P2 and also bringing the node A to the VPP level. In this way power consumption under steady state is prevented because all the nodes of the circuit assume "full" voltage values, i.e. zero or VCC=VPP. The transistor N3 is employed for decoupling the two supply voltages VCC and VPP when the latter starts to rise toward its set asymptotic level. In fact, being the gate of the transistor N3 biased at a constant value equal to VCC, when the voltage on node A rises following the rise of the VPP voltage from a VCC value to its maximum value, no current flow may take place from node A toward node IN because the Vgs (gate-sorce voltage) of the transistor N3 is equal to zero.
The latch circuit of FIG. 2 operates substantially in a way similar to that of the inverter circuit of FIG. 1, with the difference that the transistor N3 is made conducting by means of an appropriate sampling signal which is applied to the relative terminal only when the signal present at the input terminal IN of the circuit must be sampled, after which the latter signal remains stored in the circuit also after transistor N3 is cut off, being confirmed to a logic value "0" or to the logic value "1" by means of the transistor N4 or the transistor P2, respectively.
In both circuits the junctions of the p-channel transistors P2 and P1 may be subject to breakdown when the voltage VPP assumes its maximum value (gated breakdown).
A solution which is commonly resorted to for overcoming the gated breakdown problem of p-channel transistors is the so called "charge pump load". This circuit is depicted in FIG. 3 and utilizes only n-channel transistors and requires a timimg signal (phase) and therefore an oscillator for generating the latter for pumping electric charge on the output node OUT through the capacitor C and the diode connected transistor D1. Another disadvantage is that the output voltage is affected by the thresholds of the transistors D1 and T1 and becomes dependent also from the ratio between the capacitance C and the parasitic capacitance C' toward the substrate.
In CMOS circuits of the prior art p-channel transistors which are subject to the VPP voltage must necessarily be provided with implanted drain-extension regions and, more in general, special processing techniques must be resorted to in order to make these p-channel transistors capable of withstanding such a high voltage (VPP).